Serial Peripheral Interface

SPI has 4 Port signals

• SCLK - Serial Clock (master O/p)
• MISO - Master Input Slave Output (master I/p)
• MOSI - Master Output Slave Input (Master O/p)
• CS - Chip Select -active low(Master O/p)

During Each SPI clock cycle a full duplex data transmission occur

• Master send a bit on the MOSI line ; slave read it from the same line.
• Slave send a bit on MISO line ;master read it from same line

not all four transmission require all times.

Clock Polarity & Phase (CPOL & CPHA)
CPOL = 0 the base value of clock is 0

• CPHA = 0 data read on clock rising edge & data change on clock falling edge
• CPHA = 1 data read on clock falling edge & data change on clock rising edge

CPOL = 1 the base value of clock is 1

• CPHA = 0 data read on clock falling edge & data change on clock rising edge
• CPHA = 1 data read on clock rising edge & data change on clock falling edge