Gate Level Simulation - GLS

What Is Gate Level Simulation(GLS) ??



GLS is a step in design flow to ensure that the design meets functionality after place & route

Why We need GLS ??


1. To ensure that Reset release , Initialization sequence (boot up sequence) are proper in chip

2. We are not checking functionality of chip after Scan insertion after synthesis

3. STA does not check the asynchronous interface


What are the input for GLS ??


We need netlist file ,sdf file,testbenches


What is SDF ??? Structure of SDF ??

SDF means Standard Delay File . This file contains all the basic blocks of a design file with all timing information(timing contrains) like setup time ,hold time,clock to input,input to output time delay,io path deley like a lots .

Structure of SDF :

Example

Header Section

(DELAYFILE

(SDFVERSION "3.0")

(DESIGN "BIGCHIP")

(DATE "March 12, 1995 09:46")

(VENDOR "Southwestern ASIC")

(PROGRAM "Fast program")

(VERSION "1.2a")

(DIVIDER /)

(VOLTAGE 5.5:5.0:4.5)

(PROCESS "best:nom:worst")

(TEMPERATURE -40:25:125)

(TIMESCALE 100 ps)

CELL

(CELL

(CELLTYPE "BIGCHIP")

(INSTANCE top)

(DELAY

(ABSOLUTE

(INTERCONNECT mck b/c/clk (.6:.7:.9))

(INTERCONNECT d[0] b/c/d (.4:.5:.6))

)

)

)

CELL 1

(CELL

(CELLTYPE "AND2")

(INSTANCE top/b/d)

(DELAY

(ABSOLUTE

(IOPATH a y (1.5:2.5:3.4) (2.5:3.6:4.7))

(IOPATH b y (1.4:2.3:3.2) (2.3:3.4:4.3))

)

)

)

CELL 2

(CELL

(CELLTYPE "DFF")

(INSTANCE top/b/c)

(DELAY

(ABSOLUTE

(IOPATH (posedge clk) q (2:3:4) (5:6:7))

(PORT clr (2:3:4) (5:6:7))

)

)

(TIMINGCHECK

(SETUPHOLD d (posedge clk) (3:4:5) (-1:-1:-1))

(WIDTH clk (4.4:7.5:11.3))

)

)

CELL 3

.

.

.

CELL n

Note : For More details of SDF click here

What is best sdf & Worst sdf ??Why we need both ???

best sdf used for finding hold timing violations
worst sdf for for finding setup timing violations

Note :( Check this with someone else also, i think i am right,but i am not sure.If i am wrong please let me know)