There is a lots of way to design a frequency divider circuit .
Common Methord
Counters & FSM
Design a counter for that even no . The MSB will give expected output .This is the easy way to design a clock divide by any even no circuit .
Main Advantage of this less no of Flops & 50% Duty cycle
Design a FSM for expected output .
Note : You can use counters & FSM for divide by any no circuits,but odd no circuits will not give 50% duty cycle
Condition : input clock must have 50% duty cycle .
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