Digital Interview Questions - Part 2

Q: Design a transparent latch using 2:1 mux ?
A: Enable pin of latch is the select pin of Mux. 1th pin of Mux is connected is the input of Latch & oth pin is fed by output(feedback).

Q: Design a 4:1 mux using 2:1 mux
A: We need three 2:1 mux for our design . 4 input is given as the inputs of two 2:1 mux. Sel0 is connected with the sel pin of these mux. Output of these mux given to another(third) 2:1 mux & Sel1 is given as the sel pin of third 2:1 mux .

Q: What is metastability ?
A: Whenever a flipflop violate setup or hold time, flop enters to a state where the output is unpredictable . This state is known as metastable state. At the end of metastable state output will settle to 0 or 1.This process is known as metastability .

Q: Convert Nand gate to Not gate in two different ways
A:
1. Nand gate inputs are connected together and give as input of Not gate .
2. Make one input of Nand gate as high & other input as the input of Not gate.

Q:What is clock Skew ?
A: Clock skew is the phenomenon in synchronous circuit in which clock signal arrives at diferent component at different times . This may be because of interconnect wire delay or temperature variations or material imperfection or anything something like that.
There are two types of clock skew : negative clock skew and Positive clock skew,Positive skew occur when the register receive clock later than the expected time . Negative skew is just opposite to this,ie register receive clock earlier than the expected time.

Q: What is race condition ?
A: Race condition is nothing but the condition in which output of gate or flop or circuit reaches a unexpected state that can affect the other part of circuit,ie just like a glitch.
For example consider a And gate assume that same input A is fed to two inputs of gate in such a way that one one input of gate is A and other one is !A . There will be chance to produce a glitch when A changes from one state to another because of internal delay in not gate(!A).

Q: Which one is good Asynchronous reset or Synchronous reset ?
A: Its advisable to use Asynchronous reset because we can make circuit to a reset state before getting clock . Other wise there is a chance of propagation of unwanted value b4 reset occur,which is not advisable .

Q:What is the difference between Mealy and Moore state machine ??
A: Mealy and Moore are different way of designing FSM .
Mealy State machine will depends on both input and state but Moore machine depends only on State not the Input . Advantage of moore machine is that the output will always synchronous to clock ,in Mealy machine,if the input is not synchronous with the clock may results in glitches/unknown values .