Multiple Processor Running In a Single Memory

How to run multiple processor from a single memory ??

If your memory bandwidth allows you to share memory b/w two processor, we can achieve this w/o much difficult.

Concept behind sharing memory for processor

For Example, we have two processor & want to run in a single memory & Total memory address area is 0x0000_0000 to 0x4FFF_FFFF

1. Split memory address area to two (eg: 0x0000_0000 to 2FFF_FFFF and 0x3000_00000 to 0x4FFF_FFFF)
2. Load applications to base these base address(0x0000_0000 and 0x3000_0000)
3. Make processors reset vector to these base address
4. Reset the processor

It should work.

In case of Xilinx FPGA

1. Design a dual processor reference design
2. Create application for both processor
3. Open lscript.ld file change the Base address of application to differrent area
4. Build & generate elf
5. Run the applications w/o resetting the entire system.

You can see the outputs in your terminal

Note:

• Make sure that there is enough memory band width available in your system to run both application at the same time.
• Its only possible if you have Multi port DDR controller
• Its not possible to use a single DDR memory if you are going to use second memory outside the FPGA (Only Possible to use multiple processor in a single FPGA/SoC with multi port DDR controller)
  

Powerlink - Basic Concept

Ethernet POWERLINK is a deterministic real-time protocol for standard Ethernet. It is an open protocol managed by the Ethernet POWERLINK Standardization Group (EPSG). It was introduced by Austrian automation company B&R in 2001.

This protocol has nothing to do with power distribution via Ethernet cabling or power over Ethernet (PoE), power line communication or Bang & Olufsens PowerLink cable.

OverviewEthernet POWERLINK was created taking care of standard-compliance. It expands Ethernet with a mixed Polling- and Timeslicing mechanism. That brings:

Guaranteed transfer of time-critical data in very short isochronic cycles with configurable response time
Time-synchronisation of all nodes in the network with very high precision of sub-microseconds
Transmission of less timecritical data in a reserved asynchronous channel
Modern implementations reach cycle-times of under 200 µs and a time-precision (jitter) of less than 1 µs.

StandardizationPOWERLINK is standardized by the opened user- and producer-group EPSG (Ethernet POWERLINK Standardization Group) as a public standard. EPSG was founded in June 2003 as an independent association. Its focus is to leverage the advantages of Ethernet for high performance Real-Time networking systems based on the Ethernet POWERLINK Real-Time protocol, introduced by B&R end of 2001. Various working groups are focusing on different tasks like safety, technology, marketing, certification and end users. The EPSG is cooperating with leading standardization bodies and associations, like the CAN in Automation (CiA) Group and the IEC.

Physical layer
The original physical layer specified was 100Base-X Fast Ethernet (IEEE 802.3). Since end of 2006 Ethernet Powerlink with Gigabit Ethernet supporting a transmission rate ten times higher (1,000 Mbit/s) is in use. That offers a better performance for the future to extended systems with major production performance, a series of module control systems, numerous drives and completely integrated security equipment. Gigabit Ethernet is on the threshold of general dissemination in IT systems. There is no need for major change in system designs, components or cabling. Networked units that master this high transmission rate and a somewhat better cable (Cat6) must be used. The transition to higher speed Ethernet variants is always possible since Ethernet Powerlink is also attached as a standard Ethernet design and can launch its applications with standard modules such as microcomputers and FPGA modules. Usage of repeating hubs instead of switches within the Real-time domain is recommended to minimise delay and jitter. Ethernet Powerlink uses IAONA's Industrial Ethernet Planning and Installation Guide for clean cabling of industrial networks and both industrial Ethernet connectors 8P8C (RJ45) and M1 are accepted.

Data Link Layer
The Standard Ethernet Data Link Layer of Ethernet Powerlink is extended by an additional bus scheduling mechanism which secures that at a time only one node is accessing the network. The schedule is divided into an isochronous phase and an asynchronous phase. During the isochronous phase, time-critical data is transferred, while the asynchronous phase provides bandwidth for the transmission of non time-critical data. The Managing Node (MN) grants access to the physical medium via dedicated poll request messages. As a result, only one single node (CN) has access to the network at a time, which avoids collisions, usually present on Standard Ethernet. The CSMA/CD mechanism of standard Ethernet, which causes non-deterministic Ethernet behaviour, is deactivated by the collision avoidance mechanism of the Ethernet Powerlink scheduling mechanism.

Basic CycleAfter system start-up is finished, the Real-Time domain is operating under Real-Time conditions. The scheduling of the basic cycle is controlled by the Managing Node (MN). The overall cycle time depends on the amount of isochronous data, asynchronous data and the number of nodes to be polled during each cycle.

The basic cycle consists of the following phases:

Start Phase: The Managing Node is sending out a synchronization message to all nodes. The frame is called SoC - Start of Cycle.
Isochronous Phase: The Managing Node calls each node to transfer time-critical data for process or motion control by sending the Preq - Poll Request - frame. The addressed node answers with the Pres - Poll Response - frame. Since all other nodes are listening to all data during this phase, the communication system provides a producer-consumer relationship.
The time frame which includes Preq-n and Pres-n is called time slot for the addressed node.

Asynchronous Phase: The Managing Node grants the right to one particular node for sending ad-hoc data by sending out the SoA - Start of Asynchronous - frame. The addressed node will answer with ASnd. Standard IP-based protocols and addressing can be used during this phase.
The quality of the Real-Time behaviour depends on the precision of the overall basic cycle time. The length of individual phases can vary as long as the total of all phases remain within the basic cycle time boundaries. Adherence to the basic cycle time is monitored by the Managing Node. The duration of the isochronous and the asynchronous phase can be configured.








Multiplex for Bandwidth Optimization

In addition to transferring isochronous data during each basic cycle, some nodes are also able to share transfer slots for better bandwidth utilization. For that reason, the isochronous phase can distinguish between transfer slots dedicated to particular nodes, which have to send their data in every basic cycle, and slots shared by nodes to transfer their data one after the other in different cycles. Therefore less important yet still time-critical data can be transferred in longer cycles than the basic cycle. Assigning the slots during each cycle is at the discretion of the Managing Node.

Real Time Systems

Real-Time Operating Systems are systems in which certain processes or operations have guaranteed minimum and/or maximum response times. That is to say, the system ensures that it will complete operation x after time t but before time t2, whatever t and t2 are, without fail, even at the expense of other lower priority operations.

Speed, in and of itself, is not critical; the primary goal is predictability. A response time less than t may be just as bad as, or worse than, one greater than t'.

Real time operating systems are, as a general rule, only used in time-dependent embedded applications; general-purpose systems rarely if ever need to meet real-time constraints.When the do occur, real-time considerations may rule out the use of some common techniques, such as virtual memory, which may make the system's behavior less deterministic. Best-effort real-time functionality can however be useful in general purposes systems for supporting the needs of applications like digital audio workstations which demand both reliability (live recording) and low latency (real-time synthesis/processing), often at the same time.

One of the best-known Real Time OS for the x86 platform is QnX. Each system call of QnX is documented with a 'worst case completion time'.

It should be noted that "being Real Time" not necessarily means that an OS is very good at playing MPEGs, or using hardware efficiently - this is a common misunderstanding. To the contrary, for a system to provide hard real-time services implies that it can use only a limited percentage of the system's resources, including CPU time. It also fundamentally changes how software can be built for the system. For example, Rate Monotonic Scheduling - a hard real-time scheduling algorithm - can guarantee time restraints only up to 70% CPU load. Beyond that, the system has "to hit the red button" because it can no longer guarantee anything.

This implies that applications have to state their run-time requirements beforehand - how often they must be called in a second, which maximum response time is acceptable etc. All this information must be provided by the application programmer. In some cases the information is provided in implicit form, for example by arranging processes to have a certain order of priorities which allows them to meet their goals.


Bottom line, hard real time is for industrial, medical, or military systems. On your average desktop, it is misplaced

(Copied from http://wiki.osdev.org/Real-Time_Systems )

Design Advantage of FPGA & ASIC

FPGA & ASIC Design Advantages


FPGA Design Advantages

• Faster time-to-market - no layout, masks or other manufacturing steps are needed
• No upfront NRE (non recurring expenses) - costs typically associated with an ASIC design
• Simpler design cycle - due to software that handles much of the routing, placement, and timing
• More predictable project cycle - due to elimination of potential re-spins, wafer capacities, etc.
• Field reprogramability - a new bitstream can be uploaded remotely
  

ASIC Design Advantages

• Full custom capability - for design since device is manufactured to design specs
• Lower unit costs - for very high volume designs
• Smaller form factor - since device is manufactured to design specs
• Higher raw internal clock speeds

Small Query ...

Why the Earth pin in socket is bigger than other pins ????














































Ans : Resitance = resistivity * Length/Area

So Area increase Resistance will decrease & so easy path for earthing

Digital Interview Questions - Part 2

Q: Design a transparent latch using 2:1 mux ?
A: Enable pin of latch is the select pin of Mux. 1th pin of Mux is connected is the input of Latch & oth pin is fed by output(feedback).

Q: Design a 4:1 mux using 2:1 mux
A: We need three 2:1 mux for our design . 4 input is given as the inputs of two 2:1 mux. Sel0 is connected with the sel pin of these mux. Output of these mux given to another(third) 2:1 mux & Sel1 is given as the sel pin of third 2:1 mux .

Q: What is metastability ?
A: Whenever a flipflop violate setup or hold time, flop enters to a state where the output is unpredictable . This state is known as metastable state. At the end of metastable state output will settle to 0 or 1.This process is known as metastability .

Q: Convert Nand gate to Not gate in two different ways
A:
1. Nand gate inputs are connected together and give as input of Not gate .
2. Make one input of Nand gate as high & other input as the input of Not gate.

Q:What is clock Skew ?
A: Clock skew is the phenomenon in synchronous circuit in which clock signal arrives at diferent component at different times . This may be because of interconnect wire delay or temperature variations or material imperfection or anything something like that.
There are two types of clock skew : negative clock skew and Positive clock skew,Positive skew occur when the register receive clock later than the expected time . Negative skew is just opposite to this,ie register receive clock earlier than the expected time.

Q: What is race condition ?
A: Race condition is nothing but the condition in which output of gate or flop or circuit reaches a unexpected state that can affect the other part of circuit,ie just like a glitch.
For example consider a And gate assume that same input A is fed to two inputs of gate in such a way that one one input of gate is A and other one is !A . There will be chance to produce a glitch when A changes from one state to another because of internal delay in not gate(!A).

Q: Which one is good Asynchronous reset or Synchronous reset ?
A: Its advisable to use Asynchronous reset because we can make circuit to a reset state before getting clock . Other wise there is a chance of propagation of unwanted value b4 reset occur,which is not advisable .

Q:What is the difference between Mealy and Moore state machine ??
A: Mealy and Moore are different way of designing FSM .
Mealy State machine will depends on both input and state but Moore machine depends only on State not the Input . Advantage of moore machine is that the output will always synchronous to clock ,in Mealy machine,if the input is not synchronous with the clock may results in glitches/unknown values .

Gated Clocks.

Its a very good idea to turn off clocks when it is not needed. This is known as clock gating .

Why we need Clock gating ??
1. To save power consumed by combination circuit whose value is changed in each clock .
2. To save power consumed by flipflop.

Automatic clock gating is support by modern EDA tools .

There are two type of clock gating available .They are
1. Using combination circuits :-simple but glitches may come .
2. FF based circuits : Glitches free .

Circuits are given above .

Clock Muxing

Now a days we are handling multiple clock domains in our design . So we are always encounter with the problem that the switching between two clocks with out glitches.

There are two different chances,one two clock domains are totaly asynchronous or another one is one clock is multiple of another clock . In these two cases there is a chance for producing glitch while the switching between two clocks.

Usally we will disable both clock before swithing after that we change select pin & then enable clock for clock muxing.It is the safer methord of clockmuxing .

Here figures shows differents clocks muxing techniques .This is from an article in EE times. For more details click here

Digital Interview Questions - Part 1

Q : If inverted op of D ff is connected to input of ff how the flop behave ??
A : It behave as T flipflop

Q : Design a circuit for dividing input frequency by 2 ?
A : please give input frequency as the clock of T flip flop & input of flop is 1. Output will be input
clock divide by 2 .

Q : What are the different type of adder implementation ?
A : Carry Ahead,And & Xor combinational circuit , Ripple carry .

Q: Give the Truth Table for a Half Adder ?? Give gate level Implementaion of it ??
A:
A B Y Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Y = A xor B , Carry = A and B

Q : Design OR gate from 2:1 mux
A : assume that A & B are the input of OR gate . Then
Give A as sel pin of 2:1 mux , B to the 0th pin Mux & 1 to 1th pin of Mux

Q : Design a D FF from two latches ?
A : Connect two latches serialy , First latch enable pin positive level & second latch enable pin
as negative level or vice versa . Connect clock to enable pin it will work as FF .

Serial Peripheral Interface

SPI has 4 Port signals

• SCLK - Serial Clock (master O/p)
• MISO - Master Input Slave Output (master I/p)
• MOSI - Master Output Slave Input (Master O/p)
• CS - Chip Select -active low(Master O/p)

During Each SPI clock cycle a full duplex data transmission occur

• Master send a bit on the MOSI line ; slave read it from the same line.
• Slave send a bit on MISO line ;master read it from same line

not all four transmission require all times.

Clock Polarity & Phase (CPOL & CPHA)
CPOL = 0 the base value of clock is 0

• CPHA = 0 data read on clock rising edge & data change on clock falling edge
• CPHA = 1 data read on clock falling edge & data change on clock rising edge

CPOL = 1 the base value of clock is 1

• CPHA = 0 data read on clock falling edge & data change on clock rising edge
• CPHA = 1 data read on clock rising edge & data change on clock falling edge

Clk Divider Circuits

There is a lots of way to design a frequency divider circuit .

Common Methord

Counters & FSM

Design a counter for that even no . The MSB will give expected output .This is the easy way to design a clock divide by any even no circuit .
Main Advantage of this less no of Flops & 50% Duty cycle

Design a FSM for expected output .

Note : You can use counters & FSM for divide by any no circuits,but odd no circuits will not give 50% duty cycle


Condition : input clock must have 50% duty cycle .

Divide By N(Odd No) with 50% Duty Cycle

One clock counter will be Neg edge & other will be pos edge trigger
Condition : N!= 1
Disadvantage : Large No of gate count
Advanatage : 50% Duty cyle ,Simple to design.

FIFO Depth Calculation

We know that FIFO is useful for synchronizing between two clock domains .

In the case of FIFO ,FIFO depth calculation is very important. If we didn't calculate the depth of FIFO properly there is a chance to miss the data( information ).

You can find different equations & solutions from various website .

Here i am trying to explain FIFO depth calculation by a simple example.


Assume that Write Clock Frequency WClk = 200 Mhz
Read Clock Frequency RClk = 100 Mhz
No of data per 100 WClk cycle (Data rate including delay) = 80 data

So

WClk = 200Mhz = 5ns
RClk = 100 Mhz = 10ns

Total Time Taken for writing 80 data = 80*5 = 400ns .
But Time Taken for reading 80 data = 80*10 = 800 ns .

So difference b/w data write & read
same no of data = 800 -400 = 400 ns .

ie we want to store 400ns data to some position.Otherwise data will over write .

How many data will write this 400ns time = 400ns/5ns = 80 .

We have to store this 80 Data .

So we can say that FIFO should have minimum depth of 80 .

Electronic Cigaratte

Some Inventions Making People So Comfort w/o Disturbing Others.
This may help those who are not able to avoid their bad habit .

Gate Level Simulation - GLS

What Is Gate Level Simulation(GLS) ??



GLS is a step in design flow to ensure that the design meets functionality after place & route

Why We need GLS ??


1. To ensure that Reset release , Initialization sequence (boot up sequence) are proper in chip

2. We are not checking functionality of chip after Scan insertion after synthesis

3. STA does not check the asynchronous interface


What are the input for GLS ??


We need netlist file ,sdf file,testbenches


What is SDF ??? Structure of SDF ??

SDF means Standard Delay File . This file contains all the basic blocks of a design file with all timing information(timing contrains) like setup time ,hold time,clock to input,input to output time delay,io path deley like a lots .

Structure of SDF :

Example

Header Section

(DELAYFILE

(SDFVERSION "3.0")

(DESIGN "BIGCHIP")

(DATE "March 12, 1995 09:46")

(VENDOR "Southwestern ASIC")

(PROGRAM "Fast program")

(VERSION "1.2a")

(DIVIDER /)

(VOLTAGE 5.5:5.0:4.5)

(PROCESS "best:nom:worst")

(TEMPERATURE -40:25:125)

(TIMESCALE 100 ps)

CELL

(CELL

(CELLTYPE "BIGCHIP")

(INSTANCE top)

(DELAY

(ABSOLUTE

(INTERCONNECT mck b/c/clk (.6:.7:.9))

(INTERCONNECT d[0] b/c/d (.4:.5:.6))

)

)

)

CELL 1

(CELL

(CELLTYPE "AND2")

(INSTANCE top/b/d)

(DELAY

(ABSOLUTE

(IOPATH a y (1.5:2.5:3.4) (2.5:3.6:4.7))

(IOPATH b y (1.4:2.3:3.2) (2.3:3.4:4.3))

)

)

)

CELL 2

(CELL

(CELLTYPE "DFF")

(INSTANCE top/b/c)

(DELAY

(ABSOLUTE

(IOPATH (posedge clk) q (2:3:4) (5:6:7))

(PORT clr (2:3:4) (5:6:7))

)

)

(TIMINGCHECK

(SETUPHOLD d (posedge clk) (3:4:5) (-1:-1:-1))

(WIDTH clk (4.4:7.5:11.3))

)

)

CELL 3

.

.

.

CELL n

Note : For More details of SDF click here

What is best sdf & Worst sdf ??Why we need both ???

best sdf used for finding hold timing violations
worst sdf for for finding setup timing violations

Note :( Check this with someone else also, i think i am right,but i am not sure.If i am wrong please let me know)